Direct bonded copper semiconductor packages and related methods

ABSTRACT

A power semiconductor package includes a first direct bonded copper (DBC) substrate having a plurality of connection traces on a first face of the first DBC substrate. A plurality of die are coupled to the connection traces, each die coupled to one of the connection traces at a first face of the die. A second DBC substrate includes connection traces on a first face of the second DBC substrate. A second face of each die is coupled to one of the connection traces of the first face of the second DBC substrate. A cavity between the first face of the first DBC substrate and the first face of the second DBC substrate is filled with an encapsulating compound. Terminal pins may be coupled to connection traces on the first face of the first DBC substrate. More than two DBC substrates may be stacked to form a stacked power semiconductor package.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a continuation application of earlier U.S. UtilityPatent Application to Tolentino entitled “Direct Bonded CopperSemiconductor Packages and Related Methods,” application Ser. No.15/973,873, filed May 8, 2018, now pending, which is a continuationapplication of earlier U.S. Utility Patent Application to Tolentinoentitled “Direct Bonded Copper Semiconductor Packages and RelatedMethods,” application Ser. No. 15/489,998, filed Apr. 18, 2017, now U.S.Pat. No. 9,991,185, issued Jun. 5, 2018, which is a divisionalapplication of the earlier U.S. Utility Patent to Tolentino entitled“Direct Bonded Copper Semiconductor Packages and Related Methods,”application Ser. No. 14/610,115 filed Jan. 30, 2015, now U.S. Pat. No.9,659,837, issued May 23, 2017, the disclosures of each of which arehereby incorporated entirely herein by reference.

BACKGROUND 1. Technical Field

Aspects of this document relate generally to semiconductor devicepackages. Particular aspects of this document relate to powersemiconductor device packages using direct bonded copper (DBC)substrates.

2. Background Art

Semiconductor devices are often encased within (or partly within) apackage prior to use. Some packages contain a single die while otherscontain multiple die. The package offers protection to the die, such asfrom corrosion, impact and other damage, and often also includeselectrical leads or other components which connect the electricalcontacts of the die with a motherboard or other element(s). The packagemay also include components configured to dissipate heat from the dieinto a motherboard, a heat sink, or otherwise away from the die. Directbonded copper (DBC) substrates used in semiconductor packages generallyinclude a ceramic plate and either one copper layer on one side of theceramic plate or two copper layers sandwiching the ceramic platetherebetween.

SUMMARY

Implementations of power semiconductor packages may include a firstdirect bonded copper (DBC) substrate having a plurality of connectiontraces on a first face of the first DBC substrate and a plurality ofdie, each die comprising a first face coupled to one of the connectiontraces of the first face of the first DBC substrate. Implementations mayalso include a second DBC substrate having a plurality of connectiontraces on a first face of the second DBC substrate where a second faceof each of the plurality of die is coupled to one of the connectiontraces of the first face of the second DBC substrate.

Implementations of power semiconductor packages may include one, all, orany of the following:

A plurality of terminal pins, where each terminal pin is coupled to oneof the connection traces of the first face of the first DBC substrate.

The first face of each die may be coupled to the first face of the firstDBC substrate using a sintering paste.

The sintering paste may be a silver sintering paste.

The second face of each die may be coupled to the first face of thesecond DBC substrate using a sintering paste. The sintering paste may bea silver sintering paste.

The first DBC substrate may be a double-side DBC substrate including aceramic plate sandwiched between a first copper layer and a secondcopper layer, where the first copper layer includes the connectiontraces of the first DBC substrate.

The second DBC substrate may be a double-sided DBC substrate including aceramic plate sandwiched between a first copper layer and a secondcopper layer where the first copper layer includes the connection tracesof the second DBC substrate.

The power semiconductor package may include no wirebonds.

Implementations of a method of forming a power semiconductor package mayinclude coupling a first face of each of a plurality of die with one ofa plurality of connection traces of a first face of a first DBCsubstrate using sintering paste and coupling a second face of each ofthe plurality of die with one of a plurality of connection traces of afirst face of a second DBC substrate using sintering paste. The methodmay include sintering the sintering paste using heat and pressure andfilling a cavity between the first face of the first DBC substrate andthe first face of the second DBC substrate with an encapsulatingcompound forming a power semiconductor package.

Implementations of the method may include one, all, or any of thefollowing:

The sintering paste may be a silver sintering paste.

The encapsulating compound may be a silicone gel and wherein filling thecavity includes applying a vacuum at a first end of the cavity whiledispensing the encapsulating compound at a second end of the cavity.

The method may include coupling each of a plurality of terminal pins toone of the connection traces of the first face of the first DBCsubstrate.

The first DBC substrate and second DBC substrate may each include adouble DBC substrate including a ceramic plate sandwiched between afirst copper layer and a second copper layer wherein the first copperlayer of the first DBC substrate comprises the connection traces of thefirst DBC substrate and wherein the first copper layer of the second DBCsubstrate includes the connection traces of the second DBC substrate.

Implementations of a method of forming a power semiconductor package mayinclude coupling a first face of each of a first plurality of die withone of a plurality of connection traces of a first face of a first DBCsubstrate using sintering paste and coupling a second face of each ofthe first plurality of die with one of a plurality of connection tracesof a first face of a second DBC substrate using sintering paste. Themethod may include coupling a first face of each of a second pluralityof die with one of a plurality of connection traces of a second face ofthe second DBC substrate using sintering paste and coupling a secondface of each of the second plurality of die with one of a plurality ofconnection traces of a first face of a third DBC substrate usingsintering paste. The method may also include sintering the sinteringpaste using heat and pressure, filling a first cavity between the firstface of the first DBC substrate and the first face of the second DBCsubstrate, and filling a second cavity between the second face of thesecond DBC substrate and the first face of the third DBC substrate withan encapsulating compound. The method may also include coupling each ofa plurality of terminal pins to one of the connection traces of thefirst face of the first DBC substrate to form a semiconductor package.

Implementations of a method of forming a power semiconductor package mayinclude one, all, or any of the following:

The method may further include coupling a first face of each of a thirdplurality of die with one of a plurality of connection traces of asecond face of the third DBC substrate using sintering paste.

The sintering paste may be a silver sintering paste.

The encapsulating compound may be a silicone gel.

The first DBC substrate and the second DBC substrate may each include adouble DBC substrate including a ceramic plate sandwiched between afirst copper layer and a second copper layer.

The foregoing and other aspects, features, and advantages will beapparent to those artisans of ordinary skill in the art from theDESCRIPTION and DRAWINGS, and from the CLAIMS.

BRIEF DESCRIPTION OF THE DRAWINGS

Implementations will hereinafter be described in conjunction with theappended drawings, where like designations denote like elements, and:

FIG. 1 is a perspective, partial cutaway view of a first direct bondedcopper (DBC) substrate of an implementation of a power semiconductorpackage;

FIG. 2 is a perspective, partial cutaway view of a second DBC substrateof an implementation of a power semiconductor package;

FIG. 3 is a top view of the DBC substrate of FIG. 1;

FIG. 4 is a top view of the DBC substrate of FIG. 3 with sintering pastethereon;

FIG. 5 is a top view of the DBC substrate of FIG. 4 with a plurality ofdie attached thereto;

FIG. 6 it a top view of the DBC substrate of FIG. 2;

FIG. 7 is a top view of the DBC substrate of FIG. 6 with sintering pastethereon;

FIG. 8 is a top, partial see-through view of the DBC substrate of FIG. 7coupled to the DBC substrate of FIG. 5;

FIG. 9 is a side cross-section view of the assembly of FIG. 8 prior tofilling a cavity of the assembly with an encapsulating compound;

FIG. 10 is a side cross-section view of the assembly of FIG. 9 afterfilling a cavity of the assembly with an encapsulating compound;

FIG. 11 is a perspective, partial see-through view of the assembly ofFIG. 8;

FIG. 12 is a perspective, partial see-through view of the assembly ofFIG. 11 with terminal pins coupled thereto;

FIG. 13 is a side cross-section view of an implementation of a powersemiconductor package;

FIG. 14 is a side cross-section view of an implementation of a stackedpower semiconductor package;

FIG. 15 is a side cross-section view of an implementation of a powersemiconductor package; and

FIG. 16 is a side cross-section view of an implementation of a powersemiconductor package.

DESCRIPTION

This disclosure, its aspects and implementations, are not limited to thespecific components, assembly procedures or method elements disclosedherein. Many additional components, assembly procedures and/or methodelements known in the art consistent with the intended direct bondedcopper semiconductor packages and related methods will become apparentfor use with particular implementations from this disclosure.Accordingly, for example, although particular implementations aredisclosed, such implementations and implementing components may compriseany shape, size, style, type, model, version, measurement,concentration, material, quantity, method element, step, and/or the likeas is known in the art for such direct bonded copper semiconductorpackages and related methods, and implementing components and methods,consistent with the intended operation and methods.

Direct bonded copper (DBC) substrates are known in the semiconductorpackaging industry. As used herein “direct bonded copper” and “DBC”substrates refer to substrates that include a ceramictile/plate/portion/section/layer and have a sheet of copper bonded toone or both sides of the ceramic tile/section using a high-temperatureoxidation process. The copper sheet(s) and ceramic plate are brought toa controlled temperature in a gas atmosphere containing a specifiedamount of oxygen—which in implementations is about thirtyparts-per-million (ppm). The remainder of the gas may be, bynon-limiting example, nitrogen. Such conditions allow a copper-oxygeneutectic to form at the boundary(ies) of the copper sheet(s) with theceramic plate. The eutectic bonds with the copper sheet(s) and with theceramic plate. Connection traces are formed in one or both of the coppersheets. Connection traces may be formed using, by non-limiting example,wet etching, plasma etching, or the like. Connection traces may beformed before or after the heating process described above. Inimplementations the copper layer(s) of the DBC substrate that includeconnection traces are coated with nickel, gold, and/or a nickel/goldalloy. In various other implementations, the copper layer(s) of the DBCsubstrate, whether used for connection traces or not, may be coated withother metallic and/or non-metallic materials depending on downstreamprocessing, including the particular sintering pastes being employed.

Some DBCs that are double-sided DBCs (or, in other words, include twosheets of copper sandwiching the ceramic plate) include one copper sheetthat has no connection traces, but is simply a flat plate. In suchimplementations the copper sheet with connection traces may be used toelectrically connect one or more electrical contacts on the face(s) ofdie of the semiconductor package while the copper sheet withoutconnection traces may be attached to a heat sink or spreader to drawheat away from the die, or simply may be a heat sink or spreader itselfand/or may act as an electrical grounding surface for the package. Theceramic layer may be formed of, by non-limiting example, alumina(Al₂O₃), aluminum nitride (AlN), beryllium oxide (BeO), and the like.

In implementations of semiconductor packages disclosed herein one ormore DBC substrates could be substituted with an active metal brazed(AMB) substrate or an insulated metal substrate (IMS). An AMB substratemay be formed, by non-limiting example, by soldering metal foil to aceramic plate using solder paste in a high temperature, vacuumenvironment. An IMS substrate includes a metal baseplate which may beformed of, by non-limiting example, aluminum, copper, steel, or thelike. A thin dielectric layer, which may be epoxy-based, electricallyisolates the metal baseplate from, and also physically couples the metalbaseplate to, a copper layer. In some implementations of IMS substrates,the copper layer has a thickness of thirty-five to two hundred microns.The dielectric may be thin, such as about one hundred microns, due toits limited thermal conductivity compared with the ceramics used for DBCsubstrates. In other versions the dielectric may include a thermalprepreg such as a ceramic or boron filled clad which has a high voltagebreakthrough but low thermal resistance. IMS substrates which use acopper baseplate may have superior thermal performance to those with analuminum baseplate.

Referring now to FIGS. 12-14, a power semiconductor package (package) 60and a stacked power semiconductor package (package) 62 are shown. Invarious implementations, packages 60, 62 may include die 18 that arenon-power semiconductor die. When the die 18 include power semiconductordie they may be, by non-limiting example, powermetal-oxide-semiconductor field-effect transistors (power MOSFETs),insulated-gate bipolar transistors (IGBTs), and the like. Inimplementations each of the packages 60, 62 includes or is a powermodule such as, by non-limiting example, a power integrated module(PIM).

Referring now to FIG. 1, in implementations a package 60, 62 includes adirect bonded copper (DBC) substrate 2. The DBC substrate shown in FIG.1 is a double-sided DBC substrate (DBC substrate) 4 which includes aceramic plate 12 sandwiched between a first copper layer 8 and a secondcopper layer 16. The first copper layer 8 includes connection traces 10.A first face 6 of the DBC substrate 4 may thus be used forinterconnecting electrical contacts on one or more die 18 with oneanother and/or with other components internal or external to the package60, 62, while a second face 14 of the DBC substrate 4, seen in FIGS.9-10 and 13, may be used as a heat sink and/or may be coupled to a heatsink or spreader to assist in drawing heat away from one or more die 18of the package 60, 62 and/or used as an electrical ground. In particularimplementations, the DBC substrate 2 could include only a single copperlayer, which in most cases would be the layer having connection traces,though the second copper layer 16 will improve heat transfer away fromdie 18 of the package 60, 62.

Referring now to FIG. 2, in various implementations, a package 60, 62includes another direct bonded copper (DBC) substrate 28, which may be adouble-sided DBC substrate (DBC substrate) 30. A first copper layer 34on a first face 32 of the DBC substrate 30 includes connection traces36. A ceramic plate 38 is sandwiched between the first copper layer 34and a second copper layer 42. The first and second copper layers mayhave similar properties and functions to those described above withrespect to the similarly named layers of the DBC substrate 2. A firstface 32 of the DBC substrate 30 thus may be used for interconnectingelectrical contacts on one or more die 18 with one another and/or withother components internal or external to the package 60, 62, while asecond face 40 of the DBC substrate 28, seen in FIGS. 9-10 and 13, maybe used as a heat sink and/or for connection to a heat sink or spreaderto assist in drawing heat away from one or more die 18 of the package60, 62. In implementations the DBC substrate 28 could include only asingle copper layer—which in most cases would be the layer havingconnection traces, though the second copper layer 42 may improve heattransfer away from die of the package 60, 62.

Both the DBC substrate 2 and DBC substrate 28 are used in the formationof packages 60, 62. Referring to FIGS. 3-4, a conductive bonding element24 is deposited onto connection traces 10 of the first face 6 of DBCsubstrate 2. In implementations conductive bonding element 24 may be anyhigh temperature bonding element that is electrically and/or thermallyconductive. In implementations conductive bonding element 24 is asintering paste 26, such as by non-limiting example a silver sinteringpaste. In various implementations a hybrid silver sintering paste may beused which includes other conductive metallic or non-metallic elementscapable of transferring heat and/or electricity. In particularimplementations, the sintering paste may not include silver at all, butmay be composed of metallic and/or non-metallic component(s) which arecapable of transferring heat and/or electricity. Examples ofnon-metallic components which could be used in various implementationsinclude graphene. Various metals and other components of sinteringpastes may be selected depending upon the characteristics of thematerial of the particular substrates being used. In otherimplementations a different material may be used, such as a conductivehigh temperature glue, a solder paste, solder preforms, and so forth. Arepresentative example of a sintering paste which could be used is asilver sintering paste sold under the trade name LOCTITE ABLESTIK SSP2020 by Henkel AG & Company, KGaA of Düsseldorf, Germany.

While the sintering paste 26 shown in FIG. 4 is formed into x-shapes,this is only a representative example and each deposition of theconductive bonding element 24 could take on any of a variety of shapes,including: a circle, a square, and any other regular or irregular openor closed shape with or without rounded corners (where applicable) orwith or without corners at all. Likewise, the size of each deposition ofthe conductive bonding element 24 may vary according to the size of diewhich will be placed thereon, and may be smaller than or larger than theface of the die that will be attached thereto.

Referring now to FIG. 5, a plurality of die 18 is attached to the DBCsubstrate 2 using the conductive bonding element 24. In variousimplementations, each die 18 is a power semiconductor die such as apower MOSFET, an IGBT, and the like. In other implementations one ormore or all of the die 18 may be die that are not designed to performpower handling functions (non-power die).

While the figures show the conductive bonding element 24 being depositedonto the DBC substrate 2 first and the die 18 then placed thereon in thelocations of the conductive bonding element 24, the conductive bondingelement 24 could instead be deposited onto each die 18 and then each die18 could be attached to the DBC substrate 2. In the examples shown inthe figures the DBC substrate 2 includes relatively wider connectiontraces than those of the DBC substrate 28. This may assist the DBCsubstrate 2 in playing a larger role in the transfer of heat away fromthe die 18 than DBC substrate 28, with the wider connection traces 10providing superior heat transfer than the thinner connection traces 36.

As can be seen in FIGS. 9-10 and 13, the connection traces 10 are bondedto a first face 20 of the die 18. The first face 20 is the back side ofthe die which either does not include electrical contacts or whichincludes only electrical contact(s) intended to be used for grounding.Accordingly, the connection traces 10 can generally be wider as it isgenerally not required that multiple electrical contacts on the firstface 20 be electrically routed to different locations. In someimplementations there is only a single metal contact on first face 20,such as a metal pad which makes up most of the first face 20. Inimplementations the metal pad has a larger size than the electricalcontacts on the second face 22 because the pad is intended for heattransfer in addition to any electrical coupling. DBC substrate 2 thusmay be used to couple the die 18 to electrical ground for those diewhich have an electrical contact on the back side intended to beconnected to ground, and for all of the die 18 the DBC substrate 2 mayassist in heat transfer away from the back side of the die 18 throughthe conductive bonding element 24 and through the DBC substrate 2.

Referring now to FIGS. 6-7, conductive bonding element 24 is depositedonto connection traces 36 of the first face 32 of DBC substrate 28. Thesintering paste 26 shown in FIG. 7 is formed into rectangular shapes,but this is only a representative example and each deposition of theconductive bonding element 24 could take on one of a variety of formsincluding: a circle, a square, and any other regular or irregular openor closed shape with or without rounded corners (where applicable) orwith or without corners at all. Likewise, the size of each deposition ofthe conductive bonding element 24 may vary according to the size of anelectrical contact of the die 18 to which it will be bonded.

Referring now to FIG. 8, the second face 22 of each die 18, which is onan opposite side of the die 18 from the first face 20, is attached tothe DBC substrate 28 with the conductive bonding element 24. In FIG. 8 asimplified see-through illustration of DBC substrate 28 is used, whichshows the ceramic plate 38 in see-through and which does not show thesecond copper layer 42, in order to more clearly show the other elementsof FIG. 8—though the elements not shown are nevertheless present in therepresentative example. There are one or more electrical contacts on thesecond face 22 of each die 18. The second face 22 of the die is the topside of the die or, in other words, the side on which there are one ormore electrical contacts which are not intended to be connected solelyto ground (I/O, power, signal, etc.). While the electrical contacts onthe second face 22 of the die 18 are not shown in the drawings, thepractitioner of ordinary skill in the art will readily understand fromFIG. 8 how each connection trace 36 contacts one or more electricalcontacts on a second face 22 of one of the die and electrically couplesthe one or more electrical contacts of that die 18 with one or moreelectrical contacts of another die 18 and/or with one or more of theconnection traces 10 of DBC substrate 2 (such as to connect it toground).

It may also be realized from FIG. 8 that for some of the connectiontraces 36 there may need to be larger amounts of the conductive bondingelement 24 applied to portions of the connection traces 36 and less toother portions of the connection traces 36. For packages havingconnection traces 36 which are connected to one or more die 18 and whichare also connected to one or more connection traces 10 of DBC substrate2, for example, the portions of those connection traces 36 coupled tothe connection traces 10 may need more of the conductive bonding element24 as there will be a greater gap between the connection trace 36 andthe connection trace 10 than there will be between the connection traces36 and the die 18, assuming all the connection traces 10 and 36 are,respectively, of substantially uniform thickness.

In other implementations the connection traces 10 and/or the connectiontraces 36 may be of varying thicknesses, such as through selectiveetching to decrease the thickness in desired areas, so that the gapsbetween the connection traces 36 and connection traces 10 which will befilled with the conductive bonding element 24 will be closer to the sizeof, or about the same size as, or the same size as, the gaps between theconnection traces 36 and die 18 that will be filled with the conductivebonding element 24. In implementations DBC substrates discussed hereinmay include any of the features, characteristics, and properties of DBCsubstrates—such as ceramic layers of varying thickness, copper layers ofvarying thickness, and the like—disclosed in U.S. Utility applicationSer. No. 14/534,482, filed Nov. 6, 2014, listing as first inventorYusheng Lin, titled “Substrate Structures and Methods of Manufacture”(hereinafter the '482 Application), the disclosure of which is entirelyincorporated herein by reference. By non-limiting example, it may bedesirable that some connection traces 36 be thinner for finerinterconnections between electrical contacts of the die while it may bedesirable that others be thicker for greater heat transfer properties,and any of the methods disclosed in the '482 Application for formingconnection traces of varying thickness may be used to accomplish this.

In some implementations of semiconductor packages none of the connectiontraces 36 will couple to the connection traces 10, but will instead onlyinterconnect electrical contacts on the second faces 22 of the die 18with one another and/or with other elements external to the package.

While the figures show an example of the conductive bonding element 24being deposited onto the connection traces 36 and the DBC substrate 28then being coupled to the die 18, the conductive bonding element 24could instead be deposited onto each die 18 and then the DBC substrate28 coupled to the die 18. In the examples shown in the figures the DBCsubstrate 28 includes relatively thinner connection traces than those ofthe DBC substrate 2. This may allow the connection traces 36 to be usedfor finer interconnections between electrical contacts on the die 18. Ascan be seen in FIGS. 9-10 and 13, the DBC substrate 28 is bonded to asecond face 22 of the die 18. The second face 22 of any single die 18may have multiple electrical contacts which need to be routed and/orinterconnected to different elements in order for the proper function orperformance of die 18 and the package 60, 62. Wider connection tracesmay thus not be as useful for DBC substrate 28 as they may not be asuseful for finer electrical routing purposes. Nevertheless, as indicatedabove, there may be some connection traces 36 which may be thicker, orwhich may be thicker in some places, to provide greater heat transferand/or for the reasons otherwise disclosed herein. Similarly, theconnection traces 36 need not all be the same width and greater widthsmay be used in some places where the greater width will not createdifficulties in routing the electrical contacts of the second faces 22.

In implementations there may be multiple steps in applying and/or curingor otherwise completing or strengthening the bond of conductive bondingelement 24 with the various elements. When a sintering paste 26 is usedthe sintering paste 26 may be applied to the DBC substrate 2 using astencil and/or syringe, and the sintering paste 26 may then be dried inair for several minutes such as in an oven at around 120 degreesCelsius. The die 18 may then be placed on the sintering paste 26 at thissame temperature and/or the temperature may be increased to perform asnap cure of the sintering paste 26. A second layer of sintering paste26 may be deposited onto connection traces 36, and allowed to dry in airas with the first layer of sintering paste 26, and then DBC substrate 28may be placed on die 18 and a snap cure performed to form an initialbond between the two. After this a sintering step may be performed tosinter the sintering paste 26 and achieve stronger bonds between theelements coupled with sintering paste 26.

In some implementations there could be multiple sintering steps, such asa first sintering step to sinter the first layer of sintering paste 26atop the DBC substrate 2 and a second sintering step to sinter thesecond layer of sintering paste 26 atop the DBC substrate 28. In someimplementations there could be only one sintering step, so that there isa step of applying sintering paste 26 to DBC substrate 2, a drying stepfor the sintering paste 26 applied to DBC substrate 2, a step of placingthe die 18 onto DBC substrate 2, a snap cure of the sintering paste 26applied to the DBC substrate 2 to form an initial bond between DBCsubstrate 2 and the die 18, an application of sintering paste 26 to DBCsubstrate 28, a drying step for the sintering paste 26 applied to DBCsubstrate 28, a snap cure of sintering paste 26 applied to DBC substrate28 to form an initial bond between the sintering paste 26 and DBCsubstrate 28, placement of the DBC substrate 28 onto the die 18, andthen a single sintering step to sinter the sintering paste 26 betweenthe die 18 and DBC substrate 2 as well as the sintering paste 26 betweenthe die 18 and DBC substrate 28.

During the sintering step pressure is applied downwards on DBC substrate28 (and/or upwards on DBC substrate 2) and the temperature is increasedto cause the sintering of the sintering paste 26. The sintering pressuremay be applied such as using a pressure plate and may, by non-limitingexample, apply pressures ranging between 10-30 megaPascals (MPa). Thesintering temperature may be, or may be about, 230 degrees Celsius. Thetimes for these various steps may be, by non-limiting example, about tenminutes for each drying step, less than a second or tens of milliseconds(such as 50 ms) for the placement of the die or DBC substrate(s) atopother element(s), 1-5 minutes for the snap cure steps, and 1-2 minutesfor the sintering step(s). In some implementations the drying step(s)may be omitted.

DBC substrates 2 and 28 are shown in FIGS. 9-10. For ease of viewing notall of the sub-elements of the DBC substrates are shown—for instance thefirst copper layer 34 of DBC substrate 28, having the connection traces36, is shown, but the individual ceramic plates of the DBC substratesand the other copper layers are not drawn individually, though they arepresent in the DBC substrates. Similar simplified illustrations of DBCsubstrates are used in FIGS. 11-14, in which some but not all of the DBCsubstrate sub-elements are shown and in which some of the elements areshown in see-through, for clarity in seeing the other components. Eachof the DBC substrates in these figures nevertheless are double-sided DBCsubstrates having a ceramic plate sandwiched between two copper layers,although not all of the sub-elements are shown.

When the DBC substrates 2, 28 are coupled to the die 18 as disclosedherein, such as using the sintering process described herein, cavity 52is formed between DBC substrate 2 and DBC substrate 28. Cavity 52 islater filled with an encapsulating compound 44. The encapsulatingcompound 44 isolates and/or protects the die 18 and other elements ofpackages 60, 62 from, by non-limiting example, shock, vibration,moisture, corrosive agents, and the like. Encapsulating compound 44 maybe an epoxy, an underfill material, a thermosetting polymer, a siliconegel 46, polyurethane, a low glass transition temperature pottingcompound, and the like.

In the representative examples shown in the drawings the encapsulatingcompound 44 is a silicone gel 46 and is introduced into the cavity 52using an under fill process. A vacuum 50 is placed at a first end 54 ofthe cavity 52 and a dispenser 48 dispenses silicone gel 46 at a secondend 56 of the cavity 52, as shown in FIG. 9. The silicone gel 46 movestowards the first end 54 of the cavity 52 from the second end 56 usingcapillary flow action assisted by the vacuum 50. The DBC substrate 2and/or DBC substrate 28 may be heated to improve the flowcharacteristics of the silicone gel 46 during the filling process. Thevacuum 50 assists in drawing the silicone gel 46 from the second end 56towards the first end 54 to fill the cavity 52, as shown in FIG. 10, andhelps to dispense the silicone gel 46 through narrow crevices betweenDBC substrates 2 and 28, die 18, and so forth. Similar techniques areused in the industry with flip chip packaging. More than one dispenser48 and more than one vacuum 50 may be used during this process, and eachmay be placed at an appropriate location to achieve desired placement ofthe silicone gel 46 throughout the cavity 52 to completely fill it. Thusin implementations conventional vertical gel-dispense techniques may notbe needed. Conventional vertical gel-dispensing techniques may includevertical dispensing such as with a dispenser sold under the trade nameDISPENSING CELL SD-DM 402/403 by Sonderhoff Chemicals GmbH of Köln,Germany.

Other dispensing techniques that are known in the art and hereafterdiscovered may be used to fill cavity 52 with an encapsulating compound44 including epoxy underfill and other capillary action processes. Inparticular implementations, no-flow underfill processes could be used.

Encapsulating compounds 44 that are polymers, such as silicone gel 46,may undergo a curing process after being applied in order to developdesired encapsulation properties. This may involve one or more or allof: the application of heat, the application of humidity, theapplication of ultraviolet light, the presence of a catalyst, and/or thepresence of a crosslinker to link individual polymer chains together. Inimplementations encapsulating compound 44 may be or may include one ormore of the following products: a dielectric gel sold under the tradename DOW CORNING EG-3810 DIELECTRIC GEL by Dow Corning Corporation ofMidland, Mich.; a dielectric gel sold under the trade name DOW CORNINGEG-3896 KIT by Dow Corning Corporation; a dielectric gel sold under thetrade name SYLGARD 527 A&B SILICONE DIELECTRIC GEL by Dow CorningCorporation; a silicone gel sold under the trade name WACKER SILGEL 612A/B by Wacker Chemie AG of München, Germany; and the like. Specificationsheets for these four representative examples are attached herewith asAppendices A-D, the contents of each of which are hereby incorporatedentirely herein by reference, and the encapsulating compound 44 may haveany of the properties disclosed in Appendices A-D, and may likewise beapplied, cured, and otherwise prepared as disclosed in those documents,such as using any of the cure temperatures and times disclosed therein,using any two-part gel systems disclosed therein, and the like.

FIG. 11 is a representation of the configuration of DBC substrates 2, 28after the encapsulating compound 44 has been applied and, whenapplicable, cured. The encapsulating compound 44 is not shown in FIG.11, and the second copper layer 42 is also not shown, while the ceramicplate 38 is shown in see-through to show the other elements clearly. Inimplementations some or all of the connection traces 10 remain exposedafter the application and/or curing of the encapsulating compound.Referring to FIG. 12, terminal pins 58 are coupled to the connectiontraces 10 in places where the connection traces are exposed, such as bysoldering, or binding with a conductive adhesive, and so forth. In FIG.12 the encapsulating compound 44 is again not shown, the second copperlayer 42 is not shown, and the ceramic plate 12 is again shown insee-through to show the other components. In implementations theterminal pins 58 could be coupled to the connection traces 10 prior tothe encapsulation process and in such implementations it would beunnecessary to leave any of the connection traces 10 exposed after theencapsulation process.

In the examples shown in FIGS. 10-13 the terminal pins 58 are coupledonly at the connection traces 10. In such implementations one or more ofthe connection traces 10 may not be coupled to electrical ground but mayinstead provide power to the die 18, and accordingly may be coupled tothe second faces 22 of the die 18 through one or more connection traces36. In other implementations one or more of the terminal pins 58 couldbe coupled directly to one or more connection traces 36 such as toprovide power to the die 18. In such implementations there may beportions of the connection traces 36 left exposed after theencapsulation process to facilitate coupling of the terminal pins 58thereto, or the terminal pins 58 may be coupled with the connectiontraces 36 prior to the encapsulation process in which case theconnection traces 36 may be fully encapsulated with no portions exposed.

FIG. 13 is a simplified cross section view representative of package 60of FIG. 12. DBC substrates 2 and 28 are both shown in simplified formagain, wherein none of the sublayers are pointed out, though DBCsubstrates 2 and 28 in FIG. 13 are both double-sided DBC substrates witha ceramic plate sandwiched between two copper layers, one copper layerof each DBC substrate including connection traces. DBC substrate 2 inFIG. 13 is shown coupled to the first faces 20 of two die 18 withconductive bonding element 24, and the second faces 22 of the die 18 arecoupled to the DBC substrate 28 with conductive bonding element 24.Naturally the locations where the die 18 couple to the DBC substrates 2and 28 will correspond with the connection traces 10 and 36 aspreviously discussed. Encapsulating compound 44 fills the cavity 52between the DBC substrates 2 and 28. Terminal pins 58 are coupled toconnection traces 10 of DBC substrate 2.

A connector 98 has been added to DBC substrate 2, which is configured toassist in coupling an additional casing to the package 60. Connector 98may thus be a screw receiver, a snap-fit element, a friction-fitelement, an adhesive element, or the like, to allow a casing to becoupled to package 60. The casing may be a polymer casing and may havethrough-holes to allow terminal pins 58 to extend through a sidewall ofthe casing, while the rest of package 60 may be substantially housedwithin a cavity of the casing. In FIG. 13 the encapsulating compound 44is shown extending all the way to the terminal pins 58, though in otherimplementations it may cover and protect the die but may not extend allthe way to the terminal pins 58.

FIG. 14 shows a cross-section view of an example of a stacked powersemiconductor package 62 and is a representative example of how DBCsubstrates as disclosed herein may be used to stack several layers ofdie 18. The DBC substrates are again shown in simplified form. DBCsubstrate 66, which is a double-sided DBC substrate (DBC substrate) 68,includes a ceramic plate sandwiched between a copper layer on a firstface 70 and a copper layer on a second face 72, though the ceramic plateand copper layers are not explicitly shown—the ceramic plate and copperlayers instead being drawn as a single substrate layer but may bearranged like any DBC substrate disclosed herein. The copper layer onthe second face 72 includes connection traces. In other implementationsDBC substrate 66 could have only a single copper layer on the side thatfaces the die 18. DBC substrate 66 is shown coupled to the first faces20 of a first plurality 74 of die 18 with conductive bonding element 24.A DBC substrate 76 is coupled to the second faces 22 of the firstplurality 74 of die 18 with conductive bonding element 24.

While DBC substrate 76 is also shown in simplified format, it is adouble-sided DBC substrate (DBC substrate) 78 with a ceramic platesandwiched between two copper layers. DBC substrate 76 differs from DBCsubstrate 66 in that both of the copper layers of DBC substrate 76 willhave connection traces, while DBC substrate 66 may only have connectiontraces on the side that faces the die 18. Thus the second faces 22 arecoupled to connection traces of a copper layer on a first face 80 of DBCsubstrate 76 and the first faces 20 of a second plurality 84 of die 18are coupled to connection traces of a copper layer on a second face 82of DBC substrate 76 using conductive bonding element 24.

This process may be repeated a desired number of times for stacking to adesired height, with each intermediate DBC substrate being a DBCsubstrate which has connection traces in both copper layers. A top DBCsubstrate may be used atop the final layer of die 18, and the top DBCsubstrate will generally need connection traces in only one of thecopper layers (and in some implementations it may have only a singlecopper layer) which faces the die 18. In FIG. 14 the connection tracesin the bottom copper layer of DBC substrate 86 are coupled to the secondfaces 22 of the second plurality 84 of die 18 using conductive bondingelement 24. DBC substrate is a double-sided DBC substrate (DBCsubstrate) 88 and includes connection traces in a copper layer of afirst face 90 of the DBC substrate 86. In the representative example thecopper layer at a second face 92 of the DBC substrate 86 is a flatcopper sheet with no connection traces. DBC substrate 86 is drawn insimplified form in FIG. 14, so that although it has a ceramic layersandwiched between two copper layers, all these layers are simply drawnas a single substrate.

Referring still to FIG. 14, terminal pins 58 are added, an encapsulatingcompound 44 is used to fill cavities between the various DBC substratelayers and to provide protection as discussed herein, and connectors 98are added for coupling to a casing, as described herein with respect toother packages. In the representative example in which there are twolayers or pluralities of die 18 sandwiched between three DBC substrates,a first cavity 94 between DBC substrates 66 and 76 is filled withencapsulating compound 44 and a second cavity 96 between DBC substrates76 and 86 is also filled with encapsulating compound 44. Methods such asthose described elsewhere herein may be used to fill the first cavity 94and second cavity 96 with the encapsulating compound 44. Heat sinks 64may be coupled to the top and bottom DBC substrates for further heattransfer and spreading. Heat sinks 64 may be attached using a solder, anadhesive, and the like. Heat sinks 64 may also be coupled to the topand/or bottom DBC substrate(s) in any of the other packages discussedherein.

Referring to FIG. 15, in particular implementations, one or more or allof the terminal pins 58 may be omitted and instead pins 100 may becoupled to contacts on the second faces 22 of the die 18 usingconductive bonding element 24. In the package shown in FIG. 15, theleftmost conductive bonding element 24 coupled to the pin 100 is formedinto a pillar or column 102 and extends upwards through a through-holeor opening in DBC substrate 28. Column 102 may be in the form of acylindrical shape or it may take on other cross-sectional regular orirregular closed shape. Pin 100 may likewise by cylindrical or it mayhave any other cross-sectional regular or irregular closed shape. Pin100 couples to the column 102 and is formed of a conductive metal suchas, by non-limiting example, copper, aluminum, nickel, and any othermetal alloy or electrically conductive and/or metal-containing material.The leftmost column 102 is seen with a pin 100 atop it while therightmost column 102 does not have a pin 100 atop it, and may insteadact as a conductive pad for contacting with some other element. Theseare intended to be representative of variability in configurations, assome columns 102 in any given package may be topped with a pin 100 whileother columns 102 of the same package are not topped with a pin 100 asdesired. Encapsulating compound 44 is used, as shown in the figure.

FIG. 15 is a simplified representation—while there are no connectionsshown between DBC substrate 2 and DBC substrate 28 except through thedie 18, such connections may nevertheless exist in portions of thepackage as described previously with respect to FIG. 8, so that DBCsubstrate 2 could actually be grounded through a pin 100 by virtue ofcoupling of the pin 100 to an electrical ground and to the DBC substrate2 through interconnects. Although each die 18 shown in FIG. 18 is shownwith a column 102 of conductive bonding element 24 atop it, some of thesecond faces 22 of the die 18 may instead be coupled only to connectiontraces 36, similar to the die 18 shown in FIG. 13. Additionally, thoughthe DBC substrates 2 and 28 shown in FIG. 15 are in simplified form, inthe representative example each includes a ceramic plate sandwichedbetween two copper layers, as described with respect to otherimplementations disclosed in this document.

Referring to FIG. 16, in implementations one or more or all of theterminal pins 58 may be omitted and instead pins 104 may be coupled tocontacts on the second faces 22 of the die 18 using conductive bondingelement 24. In the package shown in FIG. 16, the leftmost conductivebonding element 24 coupled to the pin 104 is not formed into a column102 as was shown in the FIG. 15 example but instead is flat and the pin104 itself includes a base 108 which couples to the conductive bondingelement 24 and a column 106 which extends upwards and exits the DBCsubstrate 28 through a through hole in the DBC substrate 28. Column 106may have a cylindrical shape or any other regular or irregular closedshape. Base 108 may be circular, rectangular, square, or have any otherregular or irregular closed shape. Pin 104 is formed of a conductivemetal such as, by non-limiting example, copper, aluminum, nickel, and soforth. Plating 110 may be added to the top of the column 106. Bynon-limiting example, in implementations the pin 104 may be formed ofcopper or aluminum and the plating 110 may be formed of nickel and/ortin, though other metals and/or metal alloys may be used for either. Ifa tin or other low-melting point plating 110 is used, the plating may bereflowed with one or more other elements to form an electricalconnection as desired, such as with a printed circuit board (PCB),motherboard, power sources and/or electrical grounds, or other elements(and similar plating may be applied to pins 100 of the previous examplefor similar or other reasons). The leftmost die 18 is seen with a pin104 coupled thereto while the rightmost die 18 is simply coupled to theconnection traces 36 of the DBC substrate 28 using the conductivebonding element 24. These are intended to be representative ofvariability in configurations, as some die 18 in any given package maybe topped with a pin 104 while other die 18 of the same package mayinstead be coupled to connection traces 36 at their second faces 22 asdesired. Encapsulating compound 44 is used, as shown in the figure.

FIG. 16 is a simplified representation so that, for example, while thereare no connections shown between DBC substrate 2 and DBC substrate 28except through the die 18, such connections may nevertheless be presentin portions of the package as described herein with respect to FIG. 8,so that DBC substrate 2 could actually be grounded through a pin 104 byvirtue of coupling of the pin 104 to a ground and to the DBC substrate 2through interconnections. Although the DBC substrates 2 and 28 shown inFIG. 16 are in simplified form, in the representative example eachincludes a ceramic plate sandwiched between two copper layers, asdescribed with respect to other implementations disclosed in thisdocument.

Implementations of packages may include one or more terminal pins 58,one or more pins 100 and/or one or more pins 104, and any otherconductive connectors disclosed herein, in the same package.

As may be seen from the drawings and from the descriptions herein, invarious implementations, packages 60, 62 include no wirebonds, andinstead all of the routing is done using connection traces of one ormore DBC substrates. In implementations this increases the reliabilityof the PIM or other semiconductor power device of the package byeliminating all the possible failure modes wirebonds present when usedin a package. No conductive clips are used, in these package designs,and in such implementations the elimination of conductive clips resultsin eliminating failure modes caused by conductive clips. The ability tocool the die 18 on both sides using a DBC substrate on each sideimproves thermal performance by improving heat transfer from the die 18and may improve the performance and/or life of the die 18 and/orpackage.

As may also be deduced from the drawings and the description herein, theconnection traces 10 and connection traces 36 have complementarypatterns inasmuch as the connection traces 10 are configured to coupleto the first face 20 of each die 18 while the connection traces 36 arecoupled to the second face 22 of each die 18. Likewise the connectiontraces on the second face 72 of DBC substrate 66 are complementary tothe connection traces on the first face 80 of DBC substrate 76 inasmuchas the connection traces of the second face 72 of DBC substrate 66 areconfigured to couple to the first face 20 of each of the first plurality74 of die 18 while the connection traces of the first face 80 of DBCsubstrate 76 are coupled to the second face 22 of each of the firstplurality 74 of die 18. Likewise the connection traces on the secondface 82 of DBC substrate 76 are complementary to the connection traceson the first face 90 of DBC substrate 86 inasmuch as the connectiontraces of the second face 82 of DBC substrate 76 are configured tocouple to the first face 20 of each of the second plurality 84 of die 18while the connection traces of the first face 90 of DBC substrate 86 arecoupled to the second face 22 of each of the second plurality 84 of die18. With stacked packages that include more than two layers of die theDBC substrates will similarly have complementary connection tracesthroughout.

Conventional power integrated modules (PIMs) are not double-sided cooledbut instead have only a single thermal dissipation path, the path beingon only one side of the package. Silver sintering paste 26 has goodthermal conductivity and its use for the conductive bonding element 24may further assist with heat transfer. Improved heat transfer due tousing two or more DBC substrates for routing instead of wirebonds may beuseful for power devices in automotive applications, such as those usingstacked die 18, and in other applications. In general, the methods andelements disclosed herein for packages including die sandwiched betweentwo or more DBC substrates may result in power semiconductor devicesthat have improved thermal properties, increased life and/or improvedperformance.

In places where the description above refers to particularimplementations of direct bonded copper semiconductor packages andrelated methods and implementing components, sub-components, methods andsub-methods, it should be readily apparent that a number ofmodifications may be made without departing from the spirit thereof andthat these implementations, implementing components, sub-components,methods and sub-methods may be applied to other direct bonded coppersemiconductor packages and related methods.

What is claimed is:
 1. A power semiconductor package, comprising: afirst substrate comprising a plurality of connection traces formed in ametal layer of the first substrate; a die comprising a first facecoupled to one of the connection traces of the metal layer of the firstsubstrate; a second substrate comprising a plurality of connectiontraces formed in a metal layer of the second substrate; and a pluralityof pins, each terminal pin coupled to one of the connection traces ofthe metal layer of the first substrate, wherein the plurality of pinsextend substantially perpendicularly from the metal layer of the firstsubstrate.
 2. The power semiconductor package of claim 1, furthercomprising a silicone gel encapsulating compound filling a cavitybetween the metal layer of the first substrate and the metal layer ofthe second substrate.
 3. The power semiconductor package of claim 1,wherein a second face of the die is coupled to one of the connectiontraces of the plurality of connection traces of the metal layer of thesecond substrate.
 4. The power semiconductor package of claim 1, whereinthe first face of the die is coupled to the metal layer of the firstsubstrate using a sintering paste.
 5. The power semiconductor package ofclaim 4, wherein the sintering paste is a silver sintering paste.
 6. Thepower semiconductor package of claim 3, wherein the second face of thedie is coupled to the metal layer of the second substrate using asintering paste.
 7. The power semiconductor package of claim 6, whereinthe sintering paste is a silver sintering paste.
 8. The powersemiconductor package of claim 1, wherein the first substrate is adouble-sided substrate comprising a dielectric layer sandwiched betweenthe metal layer and a copper layer of the first substrate.
 9. The powersemiconductor package of claim 1, wherein the second substrate is adouble-sided substrate comprising a dielectric layer sandwiched betweenthe metal layer and a copper layer of the second substrate.
 10. Thepower semiconductor package of claim 1, wherein the power semiconductorpackage comprises only pins.
 11. A power semiconductor package,comprising: a first substrate comprising a plurality of connectiontraces on a first face of the first substrate; a first die comprising afirst face coupled to one of the connection traces of the first face ofthe first substrate; and a second substrate comprising a plurality ofconnection traces on a first face of the second substrate and on asecond face of the second substrate, wherein a second face of the firstdie is coupled to one of the connection traces of the first face of thesecond substrate; a second die comprising a first face coupled to one ofthe connection traces of the second face of the second substrate; and athird substrate comprising a plurality of connection traces on a firstface of the third substrate, wherein a second face of the second die iscoupled to one of the connection traces of the first face of the thirdsubstrate.
 12. The power semiconductor package of claim 11, furthercomprising an encapsulating compound filling a cavity between the firstface of the first substrate and the first face of the second substrate,and filling a cavity between the second face of the second substrate andthe first face of the third substrate with an encapsulating compound.13. The power semiconductor package of claim 11, further comprising athird die comprising a first face coupled with one of a plurality ofconnection traces of a second face of the third substrate.
 14. The powersemiconductor package of claim 11, wherein the first face and secondface of the first die and the first face and second face of the seconddie is coupled to one of the first substrate, the second substrate, andthe third substrate using a sintering paste.
 15. The power semiconductorpackage of claim 14, wherein the sintering paste is a silver sinteringpaste.
 16. The power semiconductor package of claim 11, wherein thefirst substrate is a double-sided substrate comprising a dielectriclayer sandwiched between the metal layer and a copper layer of the firstsubstrate.
 17. The power semiconductor package of claim 11, wherein thesecond substrate is a double-sided substrate comprising a dielectriclayer sandwiched between a metal layer and a copper layer of the secondsubstrate.
 18. The power semiconductor package of claim 11, wherein thethird substrate is a double-sided substrate comprising a dielectriclayer sandwiched between a metal layer and a copper layer of the thirdsubstrate.
 19. The power semiconductor package of claim 11, wherein thepower semiconductor package comprises only one or more pins.
 20. A powersemiconductor package, comprising: a first substrate comprising aplurality of connection traces formed in a metal layer of the firstsubstrate; a die comprising a first face coupled to one of theconnection traces of the metal layer of the first substrate; a secondsubstrate comprising a plurality of connection traces formed in a metallayer of the second substrate; and one or more pins, each pin coupled toone of the connection traces of the metal layer of the first substrate,where the one or more pins extend substantially perpendicularly from themetal layer of the first substrate; wherein a second face of the die iscoupled to one of the connection traces of the metal layer of the secondsubstrate.